Study track
Starter Path
Quick onboarding path for learning the basic PD vocabulary and major implementation stages.
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CMOS Fundamentals
Foundation note for CMOS behavior and MOSFET concepts with focus on intuition, vocabulary, and why device effects matter later in timing and layout decisions.
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Logic Synthesis
Synthesis-focused note describing the path from RTL intent to implementation-ready netlists, with emphasis on constraints, optimization goals, and handoff quality.
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Physical Design Inputs
Input-readiness note clarifying required design files, constraints, and library consistency checks that prevent downstream physical design noise.
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Floorplanning
Execution-oriented note for floorplanning with focus on objectives, macro placement reasoning, power planning dependencies, and early congestion risk control.
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Placement
Placement lab note centered on timing/routability tradeoffs, legalization quality, and the debug loop between congestion signals and optimization moves.
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Clock Tree Synthesis
CTS note focused on skew/latency tradeoffs, buffering strategy, and the practical checks needed before and after clock tree optimization.