PD VLSI PD Lab Fast study notes and implementation checklists

Inputs & Setup | Beginner

Physical Design Input Stack and Setup Integrity Checks

A setup-focused guide to PD inputs and library ecosystems, covering netlists, SDC, LEF and LIB, tech files, DEF, parasitics, power intent, and tool database setup with a practical startup checklist.

Estimated review time: ~40 minutes | Updated 2026-02-18

Design context and scope

This page reframes the original PD inputs article into a startup and sanity-check guide. It keeps the same data categories (logical, physical, timing, technology, and tool databases) but emphasizes dependency order and validation before the first implementation run.

Coverage map for this lab note

  • High-level view of PD input pillars: logical netlist, constraints, libraries, and technology and interconnect data.
  • Gate-level netlist and constraint files as the functional and performance contract for implementation tools.
  • Technology files, tech LEF, and interconnect and parasitic data that define physical rules and wire behavior.
  • Standard-cell library taxonomy and why multiple cell classes exist for PPA tradeoffs.
  • LEF and Liberty as complementary physical and timing and power views of the same cells.
  • DEF as a design snapshot and exchange format during implementation iterations.
  • Tool-native database environments (Milkyway and NDM style) and library-type organization inside tool setups.
  • Power intent (UPF) and CTS-related constraints that extend the baseline setup beyond netlist plus SDC.
  • Practical first-run sequencing, including why libraries and technology data must load before design import.

What you should be able to explain

  • List the minimum required files to start a PD block and explain what each one contributes.
  • Differentiate LEF, LIB, DEF, and tech files by role and typical failure mode when mismatched.
  • Create a setup-order checklist that reduces tool ingestion errors and version confusion.
  • Recognize when missing parasitic or power-intent data changes the scope of valid analysis.

Review checklist before moving ahead

  1. Verify netlist revision, SDC revision, and library versions are synchronized and documented.
  2. Check LEF and LIB naming consistency and confirm cell variants referenced by the netlist exist in libraries.
  3. Confirm technology, track, and parasitic files match the intended process and metal stack.
  4. Load libraries before design import and record any unresolved references immediately.
  5. Document optional inputs (UPF, extracted parasitics, NDR constraints) and whether they are in scope for the run.

Common watchouts

  • Most early PD failures come from data mismatch, not tool quality. Version tracking matters.
  • A successful import does not guarantee valid timing or power correlation if corners or libraries are wrong.
  • Do not treat LEF and LIB mismatches as minor warnings; they can invalidate placement, timing, and routing assumptions.

Self-check prompts

  • What breaks first when the netlist and library set are out of sync?
  • Why is load order important in ICC2-style setups?
  • When is it acceptable to proceed without extracted parasitics or full UPF data?