Design context and scope
This page keeps the topic coverage from the original logic synthesis article (goals, stages, optimization, mapping, and checks) but recasts it as a handoff-quality guide for physical design learners who need to read synthesis results critically.
Coverage map for this lab note
- What synthesis is trying to optimize and how timing, area, power, and DFT goals compete.
- Typical synthesis stages from RTL elaboration through optimization to final library-mapped netlist generation.
- Inputs and outputs: RTL, libraries, constraints, operating conditions, reports, and gate-level netlist artifacts.
- Logic optimization approaches including two-level and multi-level transformations and when they matter in practice.
- Technology mapping workflow: matching, covering, and library cell selection under constraints.
- Physical-aware and power-aware synthesis concepts, including why early optimization can help or hurt downstream PD.
- Pre-synthesis and post-synthesis qualification checks before handing off to floorplan and placement teams.
- Where synthesis sits relative to HLS and domain-specific flows in the broader EDA ecosystem.
What you should be able to explain
- Describe the synthesis flow in terms of deliverables and decisions, not just tool commands.
- Identify which reports and warnings should block a handoff to physical design.
- Explain how constraints shape optimization behavior and why poor SDC quality produces misleading QoR.
- Recognize the difference between a synthesis improvement and a change that merely shifts complexity downstream.
Review checklist before moving ahead
- Confirm library set, corners, and operating conditions used for synthesis are documented.
- Review timing, area, and power summary reports before looking at detailed violations.
- Check constraint coverage (clocks, IO delays, exceptions) and note intentional assumptions.
- Inspect major warnings: unmapped logic, inferred latches, constant nets, or black-box issues.
- Record handoff notes for PD: expected critical paths, high-fanout nets, and constraint caveats.
Common watchouts
- A clean netlist is not enough; a weak constraint set can produce a formally valid but physically difficult handoff.
- Do not compare QoR across runs without checking whether libraries, corners, or optimization priorities changed.
- Aggressive synthesis cleanup can hide structural issues that later reappear during placement or CTS.
Self-check prompts
- Why are constraints often more important than optimization switches in synthesis quality?
- What would you ask for before accepting a synthesis handoff into floorplanning?
- When should a fix remain in synthesis versus being deferred to physical implementation?