PD VLSI PD Lab Fast study notes and implementation checklists

Implementation Flow | Intermediate

Floorplan Strategy: Macro Placement, Utilization, and Early Risk Control

A floorplanning field note focused on decision quality: die and core sizing, aspect ratio, macro placement, halos and blockages, power planning, and early congestion and timing risk management.

Estimated review time: ~50 minutes | Updated 2026-02-18

Design context and scope

This guide keeps the scope of the original floorplanning article but reorganizes it around implementation decisions and qualification checks. The goal is to help you judge floorplan quality quickly before committing downstream runtime to placement and CTS.

Coverage map for this lab note

  • Why floorplanning is a make-or-break stage and how it shapes timing, routability, power, and runtime.
  • Pre-floorplan preparation: import checks, data sanity, partition boundaries, and assumptions to lock before iteration.
  • Choosing die and core size, aspect ratio, and utilization targets based on block complexity and routing expectations.
  • IO and pad placement considerations and their interaction with data flow and clock distribution paths.
  • Core row setup, cell orientation conventions, and floorplan structures that influence later placement quality.
  • Power planning dependencies (rings and straps strategy at a high level) and why they must be considered early.
  • Macro placement strategy: proximity, channel spacing, halos, blockages, and congestion-aware arrangement.
  • Timing-driven floorplan decisions and the handoff outputs expected by placement and CTS stages.
  • Qualification checklist and consequences of a poor floorplan (congestion, timing churn, ECO pain).

What you should be able to explain

  • Explain the tradeoff between utilization, routability margin, and timing ambition in a floorplan.
  • Review macro placement choices using signal flow, congestion, and power routing considerations.
  • Identify which floorplan issues must be fixed immediately versus tracked for post-placement refinement.
  • Produce a repeatable floorplan signoff checklist for early implementation iterations.

Review checklist before moving ahead

  1. Confirm die and core dimensions, aspect ratio, and utilization target are documented with rationale.
  2. Review macro adjacency and channel spacing against expected connectivity and route demand.
  3. Check halos and blockages are intentional and not masking a weak macro placement decision.
  4. Validate power-planning assumptions are compatible with macro and IO arrangement.
  5. Capture congestion and timing risk hotspots before moving to placement runs.

Common watchouts

  • Over-optimizing utilization early often creates downstream congestion that costs more than the saved area.
  • Halos and blockages can hide floorplan problems if used as a patch instead of a design choice.
  • Macro placement that ignores dataflow or clocking topology usually increases iteration count later.

Self-check prompts

  • How would you defend an aspect-ratio choice to another PD engineer?
  • When should you re-floorplan instead of trying to fix issues in placement?
  • Which floorplan outputs are most critical for a clean handoff to placement?