PD VLSI PD Lab Fast study notes and implementation checklists

Foundations | Beginner

CMOS Device Behavior for Physical Design Engineers

A rewritten foundation guide covering semiconductor behavior, PN junction intuition, MOS structures, inverter behavior, power, and timing concepts with direct relevance to later PD and STA decisions.

Estimated review time: ~45 minutes | Updated 2026-02-18

Design context and scope

This lab note reframes the old long-form CMOS fundamentals page into a study-first structure. It keeps the same technical scope (device physics to timing context) but emphasizes how each concept affects implementation, timing closure, and power analysis conversations.

Coverage map for this lab note

  • Semiconductor conduction basics and how charge movement translates to switching behavior.
  • PN junction equilibrium and bias conditions, including why junction behavior matters in parasitics and leakage discussions.
  • MOS capacitor and MOSFET structure, operating regions, and current-voltage intuition used in library timing context.
  • Threshold voltage definition, body effect, and small-geometry effects that shift delay and leakage trends.
  • CMOS inverter DC and switching behavior, sizing tradeoffs, and performance metrics used in logic design discussions.
  • Static CMOS combinational and sequential building blocks, with a bridge to standard-cell based design flows.
  • Static vs dynamic power components and common low-power thinking used later in synthesis and implementation.
  • Timing concepts (setup, hold, skew, jitter) and how transistor-level behavior eventually appears in STA reports.

What you should be able to explain

  • Explain how MOSFET behavior and threshold voltage shifts can change timing and leakage trends at the block level.
  • Describe the CMOS inverter as the reference model for delay, power, and sizing tradeoffs in digital design.
  • Connect device-level terminology to standard-cell, timing, and physical-design vocabulary used in interviews and project reviews.
  • Summarize why scaling improves speed in some cases while making leakage and variation management harder.

Review checklist before moving ahead

  1. Write a short comparison of static power and dynamic power with one example cause for each.
  2. List the MOSFET operating regions and note where digital switching spends most of its time conceptually.
  3. Describe body effect in plain language and where it may appear in timing intuition.
  4. Relate inverter sizing to delay/load tradeoff using one practical example.
  5. Define setup, hold, skew, and jitter before moving to CTS or STA guides.

Common watchouts

  • Do not treat a MOSFET as an ideal switch when reasoning about leakage, delay, or variation at advanced nodes.
  • Avoid mixing up threshold voltage reduction with unconditional speed improvement; power and leakage tradeoffs matter.
  • Do not jump to STA conclusions without separating device effects from interconnect and clocking effects.

Self-check prompts

  • Why is the CMOS inverter used so often as the baseline gate for timing and power discussions?
  • How can two cells with the same logic function show different PPA behavior?
  • What changes in the physical design flow when leakage becomes a dominant concern?